As semiconductor fabrication technology continues to improve, sizes of electronic devices are reduced, and the size and channel length of the conventional planar channel transistor also decrease correspondingly. Although the conventional planar channel transistor has been widely used in integrated circuit design, the ongoing reduction of the size and the channel length of the conventional planar channel transistor creates increasing problems with interaction between the source/drain and the carrier channel under the gate. For example, a boundary between an isolation structure and an active region results in a concentrated electric field. The concentrated electric field leads to leakage, which adversely affects the performance of the transistor by increasing power consumption, which is undesirable for many semiconductor circuit applications. Therefore, there is a need to reduce leakage current and thus to improve the performance of the transistor.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.